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2009 nidec copal electronics corp. may, 2009 ? rev. 0 1 publication order number: DP7140/d DP7140 single channel 256 tap dp with integrated eeprom and i 2 c control the DP7140 is a single channel non-volatile ?wds digital srwhqwlrphwhu (dp). this dp is frpsulvhg of a vhulh s of equal value uhvlvwru hohphqwv connected between two h[whuqdoo y accessible end srlqwv the wds srlqwv between each uhvlvwly e hohphq t can be selectively connected to the zlshu rxwsxw via lqwhuqdo cmos vzlwfkhviruplqjdolqhduwdshuhohfwurqlfsrwhqwlrphwhu . the DP7140 contains a volatile zlshu uhjlvwhu (wr) and an ?elw non ? volatile eeprom fo u wi s e u srv ition and 5 additional non ? volatile uhjlvwhuv iru jhqhudo sxusrvh data vwrudjh 3urjudpplqj riwkhuhjlvwhuvlvfrqwuroohgyld i 2 &lqwhuidfh o qsr w huxswkh w lshu srvlwlr nis uhvhw to the prvw uhfhqw value vwruhg in the non ? volatile phpru\uhjlvwhu,95 the DP7140 is available in an pb iuhh rohs frpsoldqw ?ohdg msop sdfndjh and o shu ates ove u the indust u ial whps e u atu u e u ange of ? 40 o c to +85 o c. features v 400 khz i 2 &&rpsdwleoh,qwhuidfh v 3rvlwlrq/lqhdu t dshu3rwhqwlrphwhu v end ? to ? end resistance = 50 k / 100 k v 7&5 ssp / o &w\slfdo v s wdqge\&xuuhqw $pd[ v t \slfdo w lshu5hvlvwdqfh @ 3.3 9 v o shudwlqj9 oltage = 2.5 9 to 5.5 9 v 5hjlvwhuv 8 ? bit non ? volatile eeprom v data w ulwh s wruhv v 100 yea u' ata retention v 8 ? lead msop package v pb ?iuhh5r+6&rpsoldqw1l3g$x3odwlq g figure 1. functional block diagram vcc r h r l r w wp scl sda gnd non ? volatile acr wiper ivr gp gp gp i 2 cand control volatile pin connections r w r l r h vcc gnd sda scl wp 1 (top view) see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information msop ? 83x3 z suffix case 846ad abtv = 100 k resistance abtj = 50 k resistance y = production year y = (last digit) m = production month m = (1 ? 9, a, b, c) x = production revision abtv ymx marking diagram 1 abtj ymx 1
DP7140 2 table 1. ordering information part number resistance temperature range package shipping DP7140zi ? 50 ? gt3 50 k ? 40 o c to 85 o c msop ? 8 3x3 (pb ? free) 3000/tape & reel DP7140zi ? 00 ? gt3 100 k 3000/tape & reel table 2. pin function description pin no. pin name description 1 wp memory write protect: active low 2 scl serial clock 3 sda serial data 4 gnd ground 5 r w wiper terminal 6 r l potentiometer low terminal 7 r h potentiometer high terminal 8 v cc supply voltage wp : write protect input the wp pin when tied low prevents any write operations within the device. scl: serial clock the DP7140 serial clock input pin is used to clock all data transfers into or out of the device. sda: serial data the DP7140 bidirectional serial data pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with the other open drain or open collector i/os. r h ,r l : resistor end points the set of r h and r l pins is equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the r w pin is equivalent to the wiper terminal of a mechanical potentiometer and its position is controlled by the wr register. table 3. absolute maximum ratings parameter rating unit v in supply voltage v cc to ground (note 1) ? 0.5 to +7 v terminal voltages: r h , r l , r w , sda, scl, wp ? 0.5 to v cc + 0.5 v wiper current p 6.0 ma storage temperature range ? 65 to +150 o c junction temperature range ? 40 to +150 o c lead soldering temperature (10 seconds) 300 o c esd rating hbm (human body model) 2000 v esd rating mm (machine model) 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the minimum dc input voltage is C0.5 v. during transitions, inputs may undershoot to C2.0 v for periods of less than 20 ns. m aximum dc voltage on output pins is v cc +0.5 v, which may overshoot to v cc +2.0 v for periods of less than 20 ns. table 4. recommended operating conditions parameter rating unit v cc 2.5 to 5.5 v wiper current p 3 ma temperature range ? 40 to +85 c
DP7140 3 table 5. potentiometer characteristics (note 2) (v cc = +2.5 v to +5.5 v, ? 40 c to +85 c unless otherwise specified.) parameter test conditions symbol limits units min typ max potentiometer resistance ?? 50 r pot 50 k potentiometer resistance ?? 00 r pot 100 k potentiometer resistance tolerance ( 20 % power rating 25 $ c 50 mw wiper current i w ( 3 ma wiper resistance i w = ( 3 ma v cc = 3.3 v r w 70 200 integral non ? linearity voltage divider mode inl ( 1 lsb (note 3) differential non ? linearity dnl ( 0.5 lsb (note 3) integral non ? linearity resistor mode rinl ( 1 lsb (note 3) differential non ? linearity rdnl ( 0.5 lsb (note 3) voltage on r h or r l v ss = 0 v v term v ss v cc v resolution 0.4 % zero scale error 0 0.5 2 lsb (note 4) full scale error ? 2 ? 0.5 0 lsb (note 4) temperature coefficient of r pot (notes 5, 6) tc rpot ( 100 ppm/ $ c ratiometric temp. coefficient (notes 5, 6) tc ratio 20 ppm/ $ c potentiometer capacitances (notes 5, 6) c h /c l /c w 10/10/25 pf frequency response r pot = 50 k (note 7) fc 0.4 mhz 2. latch ? up protection is provided for stresses up to 100 ma on address and data pins from ? 1 v to v cc +1 v. 3. lsb = r tot / 255 or (r h ? r l ) / 255, single pot. 4. v(r w ) 255 ? v(r w ) 0 ]/255 (r w ) 255 = 0xff, (r w ) 0 = 0x00. 5. absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 6. relative linearity is a measure of the error in step size. it is determined by the actual change in voltage between two successive tap p ositions when used as a potentiometer. 7. this parameter is tested initially and after a design or process change that affects the parameter. table 6. d.c. operating characteristics (v cc =+2.5v to+5.5v, ? 40 $ c to +85 $ c unless otherwise specified.) parameter test conditions symbol min max units power supply current volatile write & read f scl = 400 khz v cc = 5.5 v, inputs = gnd i cc1 1 ma power supply current non ? volatile write f scl = 400 khz v cc = 5.5 v, inputs = gnd i cc2 3 ma standby current v cc = 5.0 v i sb 2 a input leakage current v in = gnd to v cc i li ? 10 +10 a output leakage current v out = gnd to v cc i lo 10 a input low voltage v il ? 1 v cc x 0.3 v input high voltage v ih v cc x 0.7 v cc + 1.0 v sda output buffer low voltage v cc = 2.5 v, i ol = 4 ma v ol1 0.4 v power ? on recall minimum v cc for memory recall v por 1.4 2.0 v
DP7140 4 table 7. capacitance (t a = 25 $ c, f = 1.0 mhz, v cc = 5 v) test test conditions symbol max units input/output capacitance (sda) v i/o = 0 v c i/o (note 8) 8 pf input capacitance (scl, wp ) v in = 0 v c in (note 8) 6 pf table 8. power up timing (notes 8 and 9) parameter symbol max units power ? up to read operation t pur 1 ms power ? up to write operation t puw 1 ms 8. this parameter is tested initially and after a design or process change that affects the parameter. 9. t pur and t puw are delays required from the time v cc is stable until the specified operation can be initiated. table 9. dp timing parameter symbol min max units wiper response time after power supply stable t wrpo 50 s wiper response time: scl falling edge after last bit of wiper position data byte to wiper change t wr 20 s table 10. endurance parameter reference test method symbol min max units endurance mil ? std ? 883, test method 1033 n end 2,000,000 cycles data retention mil ? std ? 883, test method 1008 t dr 100 years table 11. a.c. characteristics (v cc =+2.5v to+5.5v, ? 40 c to +85 c unless otherwise specified.) parameter symbol min typ max units clock frequency f scl 400 khz clock high period t high 600 ns clock low period t low 1300 ns start condition setup time (for a repeated start condition) t su:sta 600 ns start condition hold time t hd:sta 600 ns data in setup time t su:dat 100 ns data in hold time t hd:dat 0 ns stop condition setup time t su:sto 600 ns time the bus must be free before a new transmission can start t buf 1300 ns wp setup time t su:wp 0 s wp hold time t hd:wp 2.5 s sda and scl rise time t r 300 ns sda and scl fall time t f 300 ns data out hold time t dh 100 ns noise suppression time constant at scl, sda inputs t i 50 ns slc low to sda data out and ack out t aa 1 s non ? volatile write cycle time t wr 4 10 ms
DP7140 5 scl sda start condition stop condition stop start clk1 scl sda in wp t su:wp t hd:wp t hd:sto, t hd:sto:nv figure 2. start and stop timing figure 3. bus timing figure 4. acknowledge timing figure 5. wp timing start scl from master data output from transmitter data output from receiver 9 8 1 bus release delay (receiver) ack setup ( * t su:dat ) ack delay ( ) t aa ) bus release delay (transmitter) t aa t dh t f t low t high scl sda in sda out t su:sta t hd:sta t hd:dat t buf t su:sto t su:dat t r
DP7140 6 device operation the DP7140 is a resistor array integrated with a i 2 c serial interface logic, an 8 ? bit volatile wiper register, and six 8 ? bit, non ? volatile memory data registers. the resistor array contains 255 separate resistive elements connected in series. the physical ends of the array are equivalent to the fixed terminals of a mechan ical potentiometer (r h and r l ). the tap positions between and at the ends of the series resistors are connected to the output wiper terminal (r w ) by cmos transistor switches. only one tap point for the potentiometer is connected to the wiper terminal at a time and is determined by the value of an 8 ? bit wiper register (wr). r h r w r l ffh feh 80h 01h 00h when power is first applied to DP7140 the wiper is set to midscale; wiper register = 80h. when the power supply becomes sufficient to read the non ? volatile memory the value stored in the initial value register (ivr) is transferred into the wiper register and the wiper moves to this new position. five additional 8 ? bit non ? volatile memory data registers are provided for general purpose data storage. data can be read or written to the volatile or the non ? volatile memory data registers via the i 2 c bus. serial bus protocol the following defines the features of the 2 ? wire bus protocol: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the DP7140 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the DP7140 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular s lave device it is requesting. DP7140 has a fixed 7 bit slave address: 0101000. the 8 th bit (lsb) is the read/write instruction bit. for a read the value is 1 and for write the value is 0. after the master sends a start condition and the slave address byte, the DP7140 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. table 12. salve address bit format b s l b s m 0 1 0 1 0 0 0 r/w acknowledge (ack) after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. DP7140 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8 ? bit byte. when the DP7140 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the DP7140 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operation in the write mode, the master device sends the start condition and the slave address information to the slave device. in '3 s case the slave address also contains a read/write command (r/w ) on the last bit of the 1st byte. after receiving an acknowledge from the slave, the master device transmits a second byte containing a memory address to select an available register. after a second acknowledge is received from the slave, the master device sends the data to be written into the selected register. the DP7140 acknowledges once more and the master
DP7140 7 generates the stop condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non ? volatile memory. if the stop condition is not sent immediately after the last ack the internal non ? volatile programming cycle doesn t start. while this internal cycle is in progress, the device will not respond to any request from the master device. write operations to volatile memory are completed during the last bit of the data byte before the slave s acknowledge. the device will be ready for another command only after a stop condition sent by master. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write operation, the DP7140 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address. if the DP7140 is still busy with the write operation, no ack will be returned. if the DP7140 has completed the write operation, an acknowledge will be returned and the host can then proceed with the next instruction operation. write protection the write protection feature allows the user to protect against inadvertent programming of the non ? volatile data registers. if the wp pin is tied to lo w, the data registers are protected and become read only. similarly, the wp pin going low after start will interrupt a nonvolatile write to data registers, while the wp pin going low after an internal write cycle has started will have no effect on any write operation. DP7140 will accept slave addresses but the data registers are protected from programming, which the device indicates by failing to send an acknowledge after data is received. read operation a read operation with a designated address consists of a three byte instruction followed by one or more data bytes (see figure 3). the master initiates the operation issuing a start, an identification byte with the r/w bit set to 0, an address byte. then the master sends a second start, and a second identification byte with the r/w bit set to 1. after each of the three bytes, the DP7140 responds with an ack. then DP7140 transmits the data byte. the master then can continue the read operation with the content of the next register by sending acknowledge or can terminate the read operation by issuing a noack followed by a stop condition after the last bit of a data byte. table 13. memory map address non ? volatile volatile register register default value 8 acr 7 reserved 6 general purpose 00h n/a 5 general purpose 00h n/a 4 general purpose 00h n/a 3 general purpose 00h n/a 2 general purpose 00h n/a 1 device id (read only) d0h n/a 0 ivr 80h wr if the master sends address 07h or addresses greater than 08h the slave responds with noack after the memory address byte. address 8: volatile access control register ? acr (i/o) the acr bit 7 (vol) toggles between non ? volatile and volatile registers accessed at address 00h. when vol is low (0), the non ? volatile ivr is accessed at address 00h. when vol is high (1), the volatile wiper register is accessed at address 00h. the initial default value for vol = 0. bit 7 6 5 4 3 2 1 0 name 0/1 vol 0 0 0 0 0 0 0 00h and 80h are the only values that should be written to address 08h. for any other value written to address 08h the slave wil l load only bit 7 but it will answer with a noack. address 7: reserved the user should not read or write to this address. DP7140 will respond with noack and it will take no action. address 07h can be accessed only in a sequential read and its content is ffh. address 6 ? 2: non ? volatile general purpose memory (i/o) 8 ? bit non ? volatile memory bit 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? general purpose memories are preprogrammed at the factory to a default value of 00h.
DP7140 8 address 1: device id (read only) bit 7 defines the dp device manufacturer; copal electronics = high (1) bit 7 6 5 4 3 2 1 0 name 1 1 0 1 0 0 0 0 a writing to address 1 has no effect. attempts to do so will return an ack but no data will be written. address 0: ivr/wr register (i/o) address 00h accesses one of two memory registers: the initial value register (ivr) or the wiper register (wr) depending upon the value of bit 7 in access control register (acr) which is at address 08h, above. wr controls the wiper s position and is a volatile memory while ivr is non ? volatile and retains its data after the chip has been powered down. writes to ivr automatically update the wr while writes to wr leave ivr unaffected. wr: wiper register = volatile. ivr: initial value register = non ? volatile. writing and reading operations: 1. if bit 7 from acr is 0 (non ? volatile): g a write operation to address 00h will write the same value in wr and ivr. g a read operation to address 00h will output the content of ivr. 2. if bit 7 from acr is 1 (volatile): g a write operation to address 00h will write in wr only. g a read operation to address 00h will output the content of wr. all changes to the wiper s position are immediate. there is no delay the wiper s movement when writing to non ? volatile memory. bit 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? ? ? ivr is preprogrammed at the factory to a default value of 80h. i 2 c serial bus instruction format table 14. i 2 c slave address bits transfer data slave address r/w bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read 51h 0 1 0 1 0 0 0 1 (r) write 50h 0 (w ) if the slave address byte sent by the host is different the device will send a noack. i 2 c protocol: (a) write data procedure with designated address. (see table 15) 1. host transfers the start condition 2. host transfers the device slave address with the write mode r/w bit (0). 3. device sends ack 4. host transfers the corresponding memory address to the device 5. device sends ack 6. host transfers the write data to the designated address 7. device sends ack 8. routines (6) and (7) are repeated based on the transfer data, and the designated address is automatically incremented* 9. host transfers the stop condition. *automatically incremented writes are not possible after a non ? volatile write.
DP7140 9 single write to either a volatile or non ? volatile register. note that bit 7 of acr determines which memory type is being written. table 15. single write (1) (2) (3) (4) (5) (6) (7) (9) start slave address 0 r/w 0 ack memory address 0 ack write data 0 ack stop a single write to either a volatile or non ? volatile register. at address 00h bit 7 of acr determines which memory type is being written. table 16. multiple writes (1) (2) (3) (4) (5) (6) (7) (8) (9) start slave address 0 r/w 0 ack memory address 0 ack write data 0 ack write data 0 ack stop multiple writes are possible only if the starting address is 08h and it should be stopped with the first nonvolatile data byte. if a nonvolatile write does not end with a stop procedure the register is not written. (b) read data procedure with designated address. 1. host transfers the start condition 2. host transfers the device slave address with the write mode r/w bit (0) 3. ack signal recognition from the device 4. host transfers the read address 5. ack signal recognition from the device 6. host transfers the re ? start condition 7. host transfers the slave address with the read mode r/w bit (1). 8. ack signal recognition from the device 9. the device transfers the read data from the designated address 10. host transfers ack signal 11. the (9) & (10) routines above are repeated if needed, and the read address is auto ? incremented 12. host transfers ack ? h to the device 13. host transfers the stop condition table 17. read data (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) start slave address 0 r/w 0 ack memory address 0 ack restart slave address 1 r/w 0 ack read data 0 ack read data 1 ack stop (c) read data procedure without a designated address. 1. host transfers the start condition 2. host transfers the device slave address with the read mode r/w bit =1 3. ack signal recognition from the device. (host then changes to receiver) 4. the device transfers data from the previous access address +1 5. host transfers ack signal 6. the (4) & (5) routines above are repeated if needed 7. host transfers ac .?+ 8. host transfers the stop condition table 18. read data w/o designated address (1) (2) (3) (4) (5) (6) (7) (8) start slave address 1 r/w 0 ack read data 0 ack read data 1 ack stop
DP7140 10 package dimensions msop 8, 3x3 e1 e a2 a1 e b d c a top view w e i v d n e w e i v e d i s l1 l2 l detail a detail a notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. symbol min nom max q a a1 a2 b c d e e1 e l 0o 6o l2 0.05 0.75 0.22 0.13 0.40 2.90 4.80 2.90 0.65 bsc 0.25 bsc 1.10 0.15 0.95 0.38 0.23 0.80 3.10 5.00 3.10 0.60 3.00 4.90 3.00 l1 0.95 ref 0.10 0.85
nidec copal electronics corp. makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. nidec copal electronics corp. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the nidec copal el ectronics corp. product could create a situation where personal injury or death may occur. nidec copal electronics corp. reserves the right to make changes to or discontinue any product or service described herein with out notice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . nidec copal electronics corp. advises customers to obtain the current version of the relevant product information before placin g orders. circuit diagrams illustrate typical semiconductor applications and may not be complete. nidec copal electronics corp. japan head office nishi-shinjuku, kimuraya bldg., 7-5-25 nishi-shinjuku, shinjuku-ku, tokyo 160-0023 phone: +81-3-3364-7055 fax: +81-3-3364-7098 www.nidec-copal-electronics.com

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